1. Field of the Invention
This invention relates generally to memory devices, and more particularly, to an approach for protecting flash memory cells from ultraviolet (UV) light.
2. Discussion of the Related Art
FIG. 1 illustrates a flash memory cell 20 in accordance with the prior art. As such, the cell includes a semiconductor substrate 22 in which source/drains 24, 26 are formed. Successive layers of gate dielectric 28, storage layer 30, dielectric 32 and control gate 34 are formed on the substrate 22. Silicide layers 36, 38, 40 are formed on the source/drains 24, 26 and the control gate 34. The memory cell 20 is programmable, upon application of appropriate voltages, by moving electrons from a source/drain through the gate dielectric 28 and into the storage layer 30, where such electrons are stored. The memory cell 20 is erasable, again upon application of appropriate voltages, by removing electrons from the storage layer 30 through the gate dielectric 28 and into a source/drain, as is well known.
Overlying this structure is a BPSG insulating layer 42, and formed on the BPSG layer 42 is a silicon-rich oxide (SiRO) layer 44 the utility of which will be described further on. A silicon dioxide cap layer 46 is provided on the SiRO layer 44. A silicon nitride layer 47 is provided on the cap layer 46, and another silicon dioxide layer 48 is provided on the silicon nitride layer 47. A conductor 50 extends through the silicon dioxide layer 48, silicon nitride layer 47, silicon dioxide cap layer 46, SiRO layer 44, BPSG layer 42, and is electrically connected to silicide layer 36. Another conductor 52 extends through the silicon dioxide layer 48, silicon nitride layer 47, silicon dioxide cap layer 46, SiRO layer 44, BPSG layer 42, and is electrically connected to silicide layer 40.
As noted above, the movement of electrons into and from the storage layer 30 determines the state of the memory cell 20. However, application of UV light to the storage layer 30 with the cell 20 in its programmed state (i.e., with electrons stored in the storage layer 30) can excite these stored electrons to undesirably cause them to dissipate and leave the storage layer 30, in turn undesirably causing the memory cell 20 to change from its programmed to its erased state. The SiRO layer 44 is a UV light blocking layer which is included for the purpose of absorbing UV light so as to shield the cell 20 (and storage layer 30) from UV light and thereby limit this problem, in turn increasing cell stability.
While the inclusion of such an SiRO layer 44 has proven effective for its desired purpose, it will be understood that improvements in this area are continually desired. For example, it has been found that the SiRO layer 44 can retain and conduct charge, for example electrons or Cu ions, which can result in undesirable conduction between conductor 50 and conductor 52 when different potentials are applied to these conductors, which can in turn cause reliability problems revealed by undertaking bias-temperature-stress (BTS) reliability tests.
Furthermore, the SiRO layer 44 has a high Si—H bonding content which has been linked to data retention issues of the cell 20, since with this high content, a high level of debonding can occur, which frees up hydrogen ions which may pass into the storage layer 30 to undesirably neutralize electrons stored in the storage layer 30.
Additionally, the etching of the SiRO layer 44 (for formation of openings therethrough for the conductors 50, 52) is a slow, time-consuming process, resulting in problems which will be described further on.
Therefore, what is needed is an approach wherein proper shielding of the memory cell from UV light is achieved, meanwhile overcoming the above problems.